1. Field of the Invention
The present invention relates to multi-chip assemblies and packages having shared inputs, such as packages for 3D integration of integrated circuit chips, and to integrated circuits for such use.
2. Description of Related Art
Three-dimensional (3D) packaging technologies have been developed in which multiple integrated circuits are integrated in a single package or other assembly. For example, multiple memory chips can be stacked to increase the density of memory within a given footprint on a printed circuit board. Typically, memory chips stacked in this way share the same control, address and/or data signals. Thus, an issue is created concerning how to access one of the stacked die at a time, such as is needed for reading and writing data to a memory array on one of the die but not on others. This can be done by special handling of the individual die before packaging, which can be costly and complex. For example, one might implement a process of marking each die on a wafer with a unique identifier ID during the manufacture of the wafer, using unique lithographic patterns for each die, such as in a metal layer, to configure a decoder on each die for use in a specific layer in a 3D stack. Then each die must be tracked according to the configuration of the decoder. This approach increases the costs of the lithographic masks and is complex to implement in practice.
U.S. Pat. No. 7,327,592, entitled Self-Identifying Stacked Die Semiconductor Components, by Silvestri, is incorporated herein by reference for disclosure of background information. According to Silvestri, the individual chips in a stack of chips are identified by the arrangement of “external control connections” implemented using micro-balls between the chips. Special decoders are connected to the micro-balls to provide for unique selection of the individual chips in the stack. This allows use of any die from a given wafer at any position in a stack. However, it requires relatively large area on each die, consumes a number of the limited amount of chip-to-chip connections and complicates the packaging process.
It is desirable to provide an integrated circuit design and a process for manufacturing by which each die in a wafer can be undistinguished during manufacture of the wafer, and can be mounted in any order in undistinguished, multi-chip packages, while allowing for distinguishing individual die during operation after packaging.